Self-Checking Decoder Using Hardware Redundancy

Abstract

A binary decoder is a combinational circuit that converts binary information from n input lines to maximum of 2n unique output lines. But there is no guaranty that the decoder always produce the correct output due to some types of faults. The characteristics of these types of faults render them undetectable by standard test strategies. The detection of intermittent faults requires the use of Concurrent Error Detection technique, which continuously monitors the operation of circuits and compares them with some known reference. Concurrent Error Detection is an important technique in the design of system in which dependability and data integrity are important. This can be achieved by incorporating some form of redundancy into the system. One method of implementing Concurrent Error Detection in Very Large Scale Integrated circuit is through the use of hardware redundancy. This paper investigates the use of hardware redundancy into unchecked system as a mean of incorporating Concurrent Error Detection into a self- checking binary decoder.